The present invention relates to a nonvolatile flash memory in which information is rewritable by electrical erasing/writing and a microcomputer incorporating the same.
JP-A-1-161469 (Laid-open on Jun. 26, 1989) describes a microcomputer having, as a programmable nonvolatile memory, an EPROM (erasable and programmable read only memory) or an EEPROM (electrically erasable and programmable read only memory) carried on a single semiconductor chip. Data and programs are held in such an on-chip nonvolatile memory of the microcomputer. Since information stored in the EPROM is erased by means of ultraviolet rays, the EPROM must be removed from a system on which it is mounted in order for the EPROM to be rewritten. The EEPROM can be erased and written electrically and therefore information stored therein can be rewritten with the EEPROM mounted on a system. However, memory cells constituting the EEPROM must be comprised of, in addition to memory devices such as NMOSs (metal nitride oxide semiconductors), selecting transistors and hence the EEPROM requires a relatively large chip occupation area being, for example, about 2.5 to 5 times as large as that of the EPROM.
JP-A-2-289997 (Laid-open on Nov. 29, 1990) describes a simultaneous erasing type EEPROM. This simultaneous erasing type EEPROM can be described as operating as a flash memory, such as described in the present specification. In the flash memory, information can be rewritten by electrical erasing and writing, each memory cell can be constructed of a single transistor as in the EPROM and, functionally, all memory cells or a block of memory cells can be erased simultaneously by electrical erasing. Accordingly, in the flash memory, information stored therein can be rewritten with the flash memory mounted on a system, the time for rewrite can be shortened by virtue of its simultaneous erasing function and contribution to reduction of the area occupied by a chip can be accomplished.
U.S. Pat. No. 5,065,364 (issued on Nov. 12, 1991) shows a flash memory of the type in which an array of electrically erasable and rewritable memory cells having control gates, drains and sources is divided into a plurality of memory blocks in a unit of data line, source lines in common to each block are led out and a voltage complying with an operation is applied separately to a source line by means of a source switch provided in each source line. At that time, ground potential is applied to the source line of a block selected for writing. A voltage VDI of, for example, 3.5V is applied to the source line of a block not selected for writing. The voltage VDI guards against word line disturbance. The word line disturbance referred to herein is a phenomenon that for example, in a memory cell having a word line conditioned for selection and a data line conditioned for unselection, the potential difference between the control gate and floating gate is increased and as a result, electric charge is discharged from floating gate to control gate to decrease the threshold of the memory cell transistor.
JP-A-59-29488 (laid-open on Feb. 16, 1991) and JP-A-3-78195 (laid-open on Apr. 3, 1991) describe an ultraviolet light-erasable EPROM in which sources of memory cells connected with the same word line are connected in common and a source potential control switch is provided for the commonly connected sources. JP-A-3-78195 (laid-open on Apr. 3, 1991) describes an ultraviolet light-erasable EPROM in which sources of memory cells connected with adjacent two word lines are connected in common and a source potential control switch is provided for each adjacent two word lines. Each of the inventions disclosed in these three references is intended to provide a solution to a problem of erroneous writing/reading caused by leak current from an unselected memory cell in an EEPROM.
U.S. application Ser. No. 07/942,028 filed Sep. 8, 1992, which is a continuation application of U.S. application Ser. No. 07/568,071 filed Aug. 16, 1990, discloses a structure of a flash memory in which sources of memory cells are connected in common for the purpose of preventing a word line disturb problem for a writing operation.
Meanwhile, JP-A-3-14272 (laid-open on Jan. 22, 1991), JP-A-3-250495 (laid-open on Nov. 8, 1991) and JP-A-2-241060 (laid-open on Sep. 25, 1990) describe division of a memory cell array in a unit to data line.